SG6932SZ【PDF 16/20 页】IC PFC CONTROLLER CCM 16SOP

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Sheet目录46

12页 13页 14页 15页 [16页]17页 18页 19页 20页

?2007 Fairchild Semiconductor Corporation

www.fairchildsemi.com

SG6932 " Rev. 1.1.3

PCB Layout

SG6932 has a single ground pin, which prevents high

sink currents in the output being returned separately.

Good high-frequency or RF layout practices should be

followed. Avoid long PCB traces and component leads.

Locate decoupling capacitors near the SG6932. A

resistor (5 ~ 20? is recommended, connected in

series from the output to the gate of the MOSFET.

Isolating the interference between the PFC and PWM

stages is also important. Figure 32 shows an example

of the PCB layout. The ground trace 1 is connected

from the ground pin to the decoupling capacitor, which

should be low impedance and as short as possible. The

ground trace 2 provides a signal ground and should be

connected directly to the decoupling capacitor C

and/or to the ground pin. The ground trace 3 is

independently tied from the decoupling capacitor to the

PFC output capacitor C

The ground in the output capacitor C

is the major

ground reference for power switching. To provide a

good ground reference and reduce the switching noise

of both the PFC and PWM stages, the ground traces 6

and 7 should be located very near and be low

impedance.

The IPFC pin is connected directly to R

through R

improve noise immunity. Do not incorrectly connect

to the ground trace 2. The IMP and ISENSE pins

should also be connected directly via the resistors R

and R

to another terminal of R

Figure 32. PCB Layout

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